Recently there has been concerted effort among researchers and engineers to protect integrated chip circuitry from the troubling effect of natural background radiation. Natural background radiation, in the form of energetic alpha particles and neutrons, has become an increasingly difficult problem to solve as transistor size shrinks with each new generation of chips. High-energy particle irradiation can corrupt data stored in memory chips, producing what engineers refer to as "soft errors". As the semiconductor industry progresses toward line widths as fine as 0.18 microns, soft errors in data pose a major challenge.
A number of different approaches have been tried to reduce soft error rates in semiconductor devices. By way of example, U.S. Pat. No. 5,691,089 discloses a transistor device for an SRAM in which a doped layer of a radiation sensitive material is formed over a substrate. The radiation sensitive material may be polyamide or a similar organic dielectric. The inventors attribute improved alpha particle immunity to the complete isolation of the SRAM array by the organic dielectric layer.
A semiconductor memory array that reduces the probability of soft errors ascribable to alpha particles is also described in U.S. Pat. Nos. 5,365,478 and 5,732,037. These patents disclose a circuit solution applied to a dynamic randomaccess memory (DRAM). Another example is provided in U.S. Pat. No. 5,065,048, which teaches specialized precharging operations that enlarge the soft error margin against alpha particle strikes in CMOS and BiCMOS logic circuits. Yet another approach to the problem of soft errors in semiconductor memory devices is described in U.S. Pat. No. 5,301,146.
FIG. 1 illustrates a simple memory cell 10 comprising field-effect devices 11-14 arranged as cross-coupled inverters. In its basic operation, memory cell 10 produces a signal at an output node 17 that represents an inverted logic signal of the input applied at node 16. Note that in FIG. 1, capacitor C.sub.TOT represents the total node capacitance at node 17 of memory cell 10. In addition, arrow 18 represents a high-energy particle, such as an alpha or neutron particle. If an alpha particle 18 passes the diffusion layer of the drain of an N-type field-effect device (e.g., field-effect device 14) when output node 17 is at a high logic level, electrons generated by the alpha particle strike are collected at the same drain. Thus, the generation of electron-hole pairs by high-energy particles has a tendency to discharge various nodes throughout a logic circuit.
Practitioners in the computer industry are now increasingly concerned about extending soft error rate protection beyond cache memories, especially in the high-end, high performance microprocessor field. For example, latch circuits have traditionally been considered robust with respect to soft errors, and latch circuit soft error rate effects have typically been considered negligible. However, as semiconductor technologies continue to advance beyond 0.25 microns, latch circuits in microprocessors have now become susceptible to soft errors. It is now known that particle strikes can cause latches to fail, leading to data corruption at the system level. Indeed, it is predicted that soft errors in latch circuits will be a significant source of errors in newer generation microprocessors. In the face of this problem, straightforward solutions--such as adding logic protection to all latches--is too costly. Thus, to ensure reliability of future CPU's there is a strong need for a new, improved latch circuit that is robust to soft errors at minimum cost.